[ipxe-devel] [PATCH 2/2] lan78xx: Adding driver for Microchip LAN78xx USB 3.0 to 10/100/1000 Ethernet device.
Ravi.Hegde at microchip.com
Ravi.Hegde at microchip.com
Wed Mar 23 19:03:23 UTC 2016
From: Ravi Hegde <ravi.hegde at microchip.com>
Adding driver for Microchip LAN78xx USB 3.0 to 10/100/1000 Ethernet device.
This driver is tested with Microsoft WDS setup.
Signed-off-by: Ravi Hegde <ravi.hegde at microchip.com>
---
src/drivers/net/lan78xx.c | 1371 +++++++++++++++++++++++++++++++++++++++++++++
src/drivers/net/lan78xx.h | 285 ++++++++++
2 files changed, 1656 insertions(+)
create mode 100644 src/drivers/net/lan78xx.c
create mode 100644 src/drivers/net/lan78xx.h
diff --git a/src/drivers/net/lan78xx.c b/src/drivers/net/lan78xx.c
new file mode 100644
index 0000000..69367ae
--- /dev/null
+++ b/src/drivers/net/lan78xx.c
@@ -0,0 +1,1371 @@
+/*
+ * Copyright (C) 2016 Ravi Hegde <ravi.hegde at microchip.com>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ * You can also choose to distribute this program under the terms of
+ * the Unmodified Binary Distribution Licence (as given in the file
+ * COPYING.UBDL), provided that you have satisfied its requirements.
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
+
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <byteswap.h>
+#include <ipxe/ethernet.h>
+#include <ipxe/usb.h>
+#include <ipxe/usbnet.h>
+#include <ipxe/profile.h>
+#include "lan78xx.h"
+
+/** @file
+ *
+ * Microchip LAN78xx USB 3.0 to 10/100/1000 Ethernet driver
+ *
+ */
+
+/** Interrupt completion profiler */
+static struct profiler lan78xx_intr_profiler __profiler =
+ { .name = "lan78xx.intr" };
+
+/** Bulk IN completion profiler */
+static struct profiler lan78xx_in_profiler __profiler =
+ { .name = "lan78xx.in" };
+
+/** Bulk OUT profiler */
+static struct profiler lan78xx_out_profiler __profiler =
+ { .name = "lan78xx.out" };
+
+/******************************************************************************
+ *
+ * Register access
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Write register (without byte-swapping)
+ *
+ * @v lan78xx LAN78xx device
+ * @v address Register address
+ * @v value Register value
+ * @ret rc Return status code
+ */
+static int lan78xx_raw_writel ( struct lan78xx_device *lan78xx,
+ unsigned int address, uint32_t value ) {
+ int rc;
+
+ /* Write register */
+ if ( ( rc = usb_control ( lan78xx->usb, LAN78XX_REGISTER_WRITE, 0,
+ address, &value, sizeof ( value ) ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not write %03x: %s\n",
+ lan78xx, address, strerror ( rc ) );
+ return rc;
+ }
+
+ return 0;
+}
+
+/**
+ * Write register
+ *
+ * @v lan78xx LAN78xx device
+ * @v address Register address
+ * @v value Register value
+ * @ret rc Return status code
+ */
+static inline __attribute__ (( always_inline )) int
+lan78xx_writel ( struct lan78xx_device *lan78xx, unsigned int address,
+ uint32_t value ) {
+ int rc;
+
+ /* Write register */
+ if ( ( rc = lan78xx_raw_writel ( lan78xx, address,
+ cpu_to_le32 ( value ) ) ) != 0 )
+ return rc;
+
+ return 0;
+}
+
+/**
+ * Read register (without byte-swapping)
+ *
+ * @v lan78xx LAN78xx device
+ * @v address Register address
+ * @ret value Register value
+ * @ret rc Return status code
+ */
+static int lan78xx_raw_readl ( struct lan78xx_device *lan78xx,
+ unsigned int address, uint32_t *value ) {
+ int rc;
+
+ /* Read register */
+ if ( ( rc = usb_control ( lan78xx->usb, LAN78XX_REGISTER_READ, 0,
+ address, value, sizeof ( *value ) ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not read %03x: %s\n",
+ lan78xx, address, strerror ( rc ) );
+ return rc;
+ }
+
+ return 0;
+}
+
+/**
+ * Read register
+ *
+ * @v lan78xx LAN78xx device
+ * @v address Register address
+ * @ret value Register value
+ * @ret rc Return status code
+ */
+static inline __attribute__ (( always_inline )) int
+lan78xx_readl ( struct lan78xx_device *lan78xx, unsigned int address,
+ uint32_t *value ) {
+ int rc;
+
+ /* Read register */
+ if ( ( rc = lan78xx_raw_readl ( lan78xx, address, value ) ) != 0 )
+ return rc;
+ le32_to_cpus ( value );
+
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * EEPROM access
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Wait for EEPROM to become idle
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_eeprom_wait ( struct lan78xx_device *lan78xx ) {
+ uint32_t e2p_cmd;
+ unsigned int i;
+ int rc;
+
+ /* Wait for EPC_BSY to become clear or timeout set */
+ for ( i = 0 ; i < LAN78XX_EEPROM_MAX_WAIT_MS ; i++ ) {
+
+ /* Read E2P_CMD and check EPC_BSY */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_E2P_CMD,
+ &e2p_cmd ) ) != 0 )
+ return rc;
+ if ( ! ( e2p_cmd & LAN78XX_E2P_CMD_EPC_BSY ) ||
+ ( e2p_cmd & LAN78XX_E2P_CMD_EPC_TIMEOUT ) )
+ break;
+
+ /* Delay */
+ mdelay ( 1 );
+ }
+
+ if ( e2p_cmd & ( LAN78XX_E2P_CMD_EPC_BSY | LAN78XX_E2P_CMD_EPC_TIMEOUT ) ) {
+ DBGC ( lan78xx, "LAN78XX %p timed out waiting for EEPROM\n",
+ lan78xx );
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/**
+ * Wait for EEPROM to become not busy
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_eeprom_confirm_not_busy ( struct lan78xx_device *lan78xx ) {
+ uint32_t e2p_cmd;
+ unsigned int i;
+ int rc;
+
+ /* Wait for EPC_BSY to become clear */
+ for ( i = 0 ; i < LAN78XX_EEPROM_MAX_WAIT_MS ; i++ ) {
+
+ /* Read E2P_CMD and check EPC_BSY */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_E2P_CMD,
+ &e2p_cmd ) ) != 0 )
+ return rc;
+ if ( ! ( e2p_cmd & LAN78XX_E2P_CMD_EPC_BSY ) )
+ return 0;
+
+ /* Delay */
+ mdelay ( 1 );
+ }
+
+ DBGC ( lan78xx, "LAN78XX %p timed out waiting for EEPROM\n",
+ lan78xx );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Read byte from EEPROM
+ *
+ * @v lan78xx LAN78xx device
+ * @v address EEPROM address
+ * @ret byte Byte read, or negative error
+ */
+static int lan78xx_eeprom_read_byte ( struct lan78xx_device *lan78xx,
+ unsigned int address ) {
+ uint32_t e2p_cmd;
+ uint32_t e2p_data;
+ int rc;
+
+ /* Wait for EEPROM to become idle */
+ if ( ( rc = lan78xx_eeprom_confirm_not_busy ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Initiate read command */
+ e2p_cmd = ( LAN78XX_E2P_CMD_EPC_BSY | LAN78XX_E2P_CMD_EPC_CMD_READ |
+ LAN78XX_E2P_CMD_EPC_ADDR ( address ) );
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_E2P_CMD,
+ e2p_cmd ) ) != 0 )
+ return rc;
+
+ /* Wait for command to complete */
+ if ( ( rc = lan78xx_eeprom_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Read EEPROM data */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_E2P_DATA,
+ &e2p_data ) ) != 0 )
+ return rc;
+
+ return LAN78XX_E2P_DATA_GET ( e2p_data );
+}
+
+/**
+ * Read data from EEPROM
+ *
+ * @v lan78xx LAN78xx device
+ * @v address EEPROM address
+ * @v data Data buffer
+ * @v len Length of data
+ * @ret rc Return status code
+ */
+static int lan78xx_eeprom_read ( struct lan78xx_device *lan78xx,
+ unsigned int address, void *data,
+ size_t len ) {
+ uint8_t *bytes;
+ uint32_t hw_cfg;
+ int byte;
+ int rc;
+
+ /* For LAN7800 the LED pins are muxed with the CLK and DO
+ pins. Disable LED0 and LED1 while accessing EEPROM */
+ if ( LAN78XX_ID_GET(lan78xx->chip_id) == LAN78XX_ID_LAN7800 ) {
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_HW_CFG,
+ &hw_cfg ) ) != 0 )
+ return rc;
+
+ if ( hw_cfg & ( LAN78XX_HW_CFG_LED0_EN | LAN78XX_HW_CFG_LED1_EN ) ) {
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_HW_CFG,
+ ( hw_cfg & ~( LAN78XX_HW_CFG_LED0_EN |
+ LAN78XX_HW_CFG_LED1_EN ) ) ) ) != 0 )
+ return rc;
+ }
+ }
+
+ /* Read bytes */
+ for ( bytes = data ; len-- ; address++, bytes++ ) {
+ byte = lan78xx_eeprom_read_byte ( lan78xx, address );
+ if ( byte < 0 )
+ break;
+ *bytes = ( uint8_t ) byte;
+ }
+
+ /* Restore the LED configurations if enabled */
+ if ( ( LAN78XX_ID_GET(lan78xx->chip_id) == LAN78XX_ID_LAN7800 ) &&
+ ( hw_cfg & ( LAN78XX_HW_CFG_LED0_EN | LAN78XX_HW_CFG_LED1_EN ) ) ) {
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_HW_CFG,
+ hw_cfg ) ) != 0 )
+ return rc;
+ }
+
+ if ( byte < 0)
+ return byte;
+
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * OTP access
+ *
+ ******************************************************************************
+ */
+/**
+ * Wait for OTP to become idle
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_otp_wait ( struct lan78xx_device *lan78xx ) {
+ uint32_t otp_status;
+ unsigned int i;
+ int rc;
+
+ /* Wait for EPC_BSY to become clear */
+ for ( i = 0 ; i < LAN78XX_OTP_MAX_WAIT_MS ; i++ ) {
+
+ /* Read BUSY bit in OTP status register */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_OTP_STATUS,
+ &otp_status ) ) != 0 )
+ return rc;
+ if ( ! ( otp_status & LAN78XX_OTP_STATUS_BUSY ) )
+ return 0;
+
+ /* Delay */
+ mdelay ( 1 );
+ }
+
+ DBGC ( lan78xx, "LAN78XX %p timed out waiting for otp\n",
+ lan78xx );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Wait for OTP to to be operational from power down state
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_otp_wake_from_power_down ( struct lan78xx_device *lan78xx ) {
+ uint32_t otp_pwdn;
+ unsigned int i;
+ int rc;
+
+ /* check otp power down bit */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_OTP_PWR_DN,
+ &otp_pwdn ) ) != 0 )
+ return rc;
+
+ if ( otp_pwdn & LAN78XX_OTP_PWR_DN_PWRDN ) {
+ /* Clear power down bit */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_OTP_PWR_DN,
+ 0 ) ) != 0 )
+ return rc;
+
+ /* Wait for PWDN bit to become clear */
+ for ( i = 0 ; i < LAN78XX_OTP_MAX_WAIT_MS ; i++ ) {
+
+ /* check otp power down bit */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_OTP_PWR_DN,
+ &otp_pwdn ) ) != 0 )
+ return rc;
+ if ( ! ( otp_pwdn & LAN78XX_OTP_PWR_DN_PWRDN ) )
+ return 0;
+
+ /* Delay */
+ mdelay ( 1 );
+ }
+ }
+
+ DBGC ( lan78xx, "LAN78XX %p timed out waiting for clearing pwdn bit\n",
+ lan78xx );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Read byte from OTP
+ *
+ * @v lan78xx LAN78xx device
+ * @v address EEPROM address
+ * @ret byte Byte read, or negative error
+ */
+static int lan78xx_otp_read_byte ( struct lan78xx_device *lan78xx,
+ unsigned int address ) {
+ uint32_t otp_data;
+ int rc;
+
+ /* Wait for OTP to become idle */
+ if ( ( rc = lan78xx_otp_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Initiate read command */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_OTP_ADDR_HIGH,
+ LAN78XX_OTP_ADDR_HIGH_1_0 ( address) ) ) != 0 )
+ return rc;
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_OTP_ADDR_LOW,
+ LAN78XX_OTP_ADDR_LOW_7_0 ( address) ) ) != 0 )
+ return rc;
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_OTP_FUNC_CMD,
+ LAN78XX_OTP_FUNC_CMD_READ ) ) != 0 )
+ return rc;
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_OTP_CMD_GO,
+ LAN78XX_OTP_CMD_GO_GO ) ) != 0 )
+ return rc;
+
+ /* Wait for command to complete */
+ if ( ( rc = lan78xx_otp_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Read OTP data */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_OTP_RD_DATA,
+ &otp_data ) ) != 0 )
+ return rc;
+
+ return LAN78XX_OTP_DATA_GET ( otp_data );
+}
+
+/**
+ * Read data from OTP
+ *
+ * @v lan78xx LAN78xx device
+ * @v address OTP address
+ * @v data Data buffer
+ * @v len Length of data
+ * @ret rc Return status code
+ */
+static int lan78xx_otp_read ( struct lan78xx_device *lan78xx,
+ unsigned int address, void *data,
+ size_t len ) {
+ uint8_t *bytes;
+ int sig;
+ int byte;
+ int rc;
+
+ if ( ( rc = lan78xx_otp_wake_from_power_down ( lan78xx ) ) != 0 )
+ return rc;
+
+ if ( ( sig = lan78xx_otp_read_byte ( lan78xx, 0 ) ) < 0 )
+ return rc;
+
+ /* Decide the offset based on the signature */
+ if ( sig == LAN78XX_OTP_INDICATOR_1 )
+ address = address;
+ else if ( sig == LAN78XX_OTP_INDICATOR_2 )
+ address += 0x100;
+ else
+ return -EINVAL;
+
+ /* Read bytes */
+ for ( bytes = data ; len-- ; address++, bytes++ ) {
+ byte = lan78xx_otp_read_byte ( lan78xx, address );
+ if ( byte < 0 )
+ return byte;
+ *bytes = ( uint8_t ) byte;
+ }
+
+ return 0;
+}
+
+/**
+ * Read MAC address from either from EEPROM/OTP/value stored in register
+ * or else generate random MAC address.
+ *
+ * @v lan78xx LAN78xx device
+ * @v hw_addr Hardware address to fill in
+ * @ret rc Return status code
+ */
+static int lan78xx_get_mac_address ( struct lan78xx_device *lan78xx,
+ uint8_t *hw_addr ) {
+ uint32_t addrh, addrl;
+
+ lan78xx_eeprom_read ( lan78xx, LAN78XX_EEPROM_MAC,
+ hw_addr, ETH_ALEN );
+ /* Check mac address is valid */
+ if ( ! is_valid_ether_addr ( hw_addr ) ) {
+ /* Check to see OTP is present */
+ lan78xx_otp_read ( lan78xx, LAN78XX_EEPROM_MAC,
+ hw_addr, ETH_ALEN );
+ /* Check mac address is valid */
+ if ( ! is_valid_ether_addr ( hw_addr ) ) {
+ /* Check whether ADDRH/L has valid MAC address
+ programmed by pre-OS */
+ lan78xx_readl ( lan78xx, LAN78XX_RX_ADDRH, &addrh );
+ lan78xx_readl ( lan78xx, LAN78XX_RX_ADDRL, &addrl );
+
+ hw_addr[0] = addrl & 0xFF;
+ hw_addr[1] = ( addrl >> 8 ) & 0xFF;
+ hw_addr[2] = ( addrl >> 16 ) & 0xFF;
+ hw_addr[3] = ( addrl >> 24 ) & 0xFF;
+ hw_addr[4] = addrh & 0xFF;
+ hw_addr[5] = ( addrh >> 8 )& 0xFF;
+
+ if ( ! is_valid_ether_addr ( hw_addr ) ) {
+ /* Else, generate a random MAC address */
+ eth_random_addr ( hw_addr );
+ }
+ }
+ }
+
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * MII access
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Wait for MII to become idle
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_mii_wait ( struct lan78xx_device *lan78xx ) {
+ uint32_t mii_access;
+ unsigned int i;
+ int rc;
+
+ /* Wait for MIIBZY to become clear */
+ for ( i = 0 ; i < LAN78XX_MII_MAX_WAIT_MS ; i++ ) {
+
+ /* Read MII_ACCESS and check MIIBZY */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_MII_ACCESS,
+ &mii_access ) ) != 0 )
+ return rc;
+ if ( ! ( mii_access & LAN78XX_MII_ACCESS_MIIBZY ) )
+ return 0;
+
+ /* Delay */
+ mdelay ( 1 );
+ }
+
+ DBGC ( lan78xx, "LAN78XX %p timed out waiting for MII\n",
+ lan78xx );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Read from MII register
+ *
+ * @v mii MII interface
+ * @v reg Register address
+ * @ret value Data read, or negative error
+ */
+static int lan78xx_mii_read ( struct mii_interface *mii, unsigned int reg ) {
+ struct lan78xx_device *lan78xx =
+ container_of ( mii, struct lan78xx_device, mii );
+ uint32_t mii_access;
+ uint32_t mii_data;
+ int rc;
+
+ /* Wait for MII to become idle */
+ if ( ( rc = lan78xx_mii_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Initiate read command */
+ mii_access = ( LAN78XX_MII_ACCESS_PHY_ADDR ( lan78xx->phy_addr ) |
+ LAN78XX_MII_ACCESS_MIIRINDA ( reg ) |
+ LAN78XX_MII_ACCESS_MIIBZY );
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MII_ACCESS,
+ mii_access ) ) != 0 )
+ return rc;
+
+ /* Wait for command to complete */
+ if ( ( rc = lan78xx_mii_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Read MII data */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_MII_DATA,
+ &mii_data ) ) != 0 )
+ return rc;
+
+ return LAN78XX_MII_DATA_GET ( mii_data );
+}
+
+/**
+ * Write to MII register
+ *
+ * @v mii MII interface
+ * @v reg Register address
+ * @v data Data to write
+ * @ret rc Return status code
+ */
+static int lan78xx_mii_write ( struct mii_interface *mii, unsigned int reg,
+ unsigned int data ) {
+ struct lan78xx_device *lan78xx =
+ container_of ( mii, struct lan78xx_device, mii );
+ uint32_t mii_access;
+ uint32_t mii_data;
+ int rc;
+
+ /* Wait for MII to become idle */
+ if ( ( rc = lan78xx_mii_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ /* Write MII data */
+ mii_data = LAN78XX_MII_DATA_SET ( data );
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MII_DATA,
+ mii_data ) ) != 0 )
+ return rc;
+
+ /* Initiate write command */
+ mii_access = ( LAN78XX_MII_ACCESS_PHY_ADDR ( lan78xx->phy_addr ) |
+ LAN78XX_MII_ACCESS_MIIRINDA ( reg ) |
+ LAN78XX_MII_ACCESS_MIIWNR |
+ LAN78XX_MII_ACCESS_MIIBZY );
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MII_ACCESS,
+ mii_access ) ) != 0 )
+ return rc;
+
+ /* Wait for command to complete */
+ if ( ( rc = lan78xx_mii_wait ( lan78xx ) ) != 0 )
+ return rc;
+
+ return 0;
+}
+
+/** MII operations */
+static struct mii_operations lan78xx_mii_operations = {
+ .read = lan78xx_mii_read,
+ .write = lan78xx_mii_write,
+};
+
+/**
+ * Check link status
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_check_link ( struct lan78xx_device *lan78xx ) {
+ struct net_device *netdev = lan78xx->netdev;
+ int intr;
+ int rc;
+
+ /* Read PHY interrupt source */
+ intr = mii_read ( &lan78xx->mii, LAN78XX_MII_PHY_INTR_SOURCE );
+ if ( intr < 0 ) {
+ rc = intr;
+ DBGC ( lan78xx, "LAN78XX %p could not get PHY interrupt "
+ "source: %s\n", lan78xx, strerror ( rc ) );
+ return rc;
+ }
+
+ /* Acknowledge PHY interrupt */
+ if ( ( rc = mii_write ( &lan78xx->mii, LAN78XX_MII_PHY_INTR_SOURCE,
+ intr ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not acknowledge PHY "
+ "interrupt: %s\n", lan78xx, strerror ( rc ) );
+ return rc;
+ }
+
+ /* Check link status */
+ if ( ( rc = mii_check_link ( &lan78xx->mii, netdev ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not check link: %s\n",
+ lan78xx, strerror ( rc ) );
+ return rc;
+ }
+
+ DBGC ( lan78xx, "LAN78XX %p link %s (intr %#04x)\n",
+ lan78xx, ( netdev_link_ok ( netdev ) ? "up" : "down" ), intr );
+
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * Device reset
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Reset device
+ *
+ * @v lan78xx LAN78xx device
+ * @ret rc Return status code
+ */
+static int lan78xx_reset ( struct lan78xx_device *lan78xx ) {
+ uint32_t reg;
+ uint32_t chip_id;
+ int rc, i;
+
+ /* Reset device */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_HW_CFG,
+ ® ) ) != 0 )
+ return rc;
+
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_HW_CFG,
+ reg | LAN78XX_HW_CFG_LRST ) ) != 0 )
+ return rc;
+
+ /* Wait for reset to complete */
+ for ( i = 0; i < LAN78XX_RESET_MAX_WAIT_MS; i++ ) {
+
+ /* Check that reset has completed */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_HW_CFG,
+ ® ) ) != 0 )
+ return rc;
+ if ( reg & LAN78XX_HW_CFG_LRST ) {
+ mdelay( 1 );
+ continue;
+ }
+ break;
+ }
+
+ if ( i >= LAN78XX_RESET_MAX_WAIT_MS ) {
+ DBGC ( lan78xx, "LAN78XX %p failed to reset\n", lan78xx );
+ return -ETIMEDOUT;
+ }
+
+ /* Reset phy */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_PMT_CTL,
+ ® ) ) != 0 )
+ return rc;
+
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_PMT_CTL,
+ reg | LAN78XX_PMT_CTL_PHY_RST ) ) != 0 )
+ return rc;
+
+ /* Wait for reset to complete */
+ for ( i = 0; i < LAN78XX_RESET_MAX_WAIT_MS; i++ ) {
+
+ /* Check that reset has completed */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_PMT_CTL,
+ ® ) ) != 0 )
+ return rc;
+ if ( (reg & LAN78XX_PMT_CTL_PHY_RST ) ||
+ ( ! ( reg & LAN78XX_PMT_CTL_DEV_RDY ) ) ) {
+ mdelay( 1 );
+ continue;
+ }
+ break;
+ }
+
+ if ( i >= LAN78XX_RESET_MAX_WAIT_MS ) {
+ DBGC ( lan78xx, "LAN78XX %p failed to reset phy, "
+ "pmt_ctl: 0x%8x\n", lan78xx, reg );
+ return -ETIMEDOUT;
+ }
+
+ /* Check whether we support this chip. Some part numbers (with
+ external phy) are not supported by this driver) */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_ID_REV,
+ &chip_id ) ) != 0 )
+ return rc;
+
+ if ( !( (LAN78XX_ID_GET(chip_id) == LAN78XX_ID_LAN7800) ||
+ (LAN78XX_ID_GET(chip_id) == LAN78XX_ID_LAN7850) ) ) {
+ DBGC ( lan78xx, "LAN78XX %p unsupported device 0x%08x\n",
+ lan78xx, chip_id );
+ return -ENODEV;
+ }
+
+ /* Save chip id */
+ lan78xx->chip_id = chip_id;
+
+ /* Internal phy address 1 */
+ lan78xx->phy_addr = 1;
+
+ return 0;
+}
+
+static int lan78xx_phy_init ( struct lan78xx_device *lan78xx ) {
+ int rc;
+ int val;
+
+ /* Auto-neg advertisement */
+ if ( ( val = mii_read ( &lan78xx->mii, MII_ADVERTISE ) ) < 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error reading phy adv register\n",
+ lan78xx );
+ return val;
+ }
+
+ val |= ( ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM );
+
+ if ( ( rc = mii_write ( &lan78xx->mii, MII_ADVERTISE, val ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error writing phy adv register\n",
+ lan78xx );
+ return rc;
+ }
+
+ /* 1000BASE-T Control register setup */
+ if ( ( val = mii_read ( &lan78xx->mii, MII_CTRL1000 ) ) < 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error reading ctrl1000 register\n",
+ lan78xx );
+ return val;
+ }
+
+ /* Only enable 1000 full */
+ val |= ADVERTISE_1000FULL;
+ val &= ~ADVERTISE_1000HALF;
+
+ if ( ( rc = mii_write ( &lan78xx->mii, MII_CTRL1000, val ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error writing ctrl1000 register\n",
+ lan78xx );
+ return rc;
+ }
+
+ /* Restart auto negotiation */
+ if ( ( val = mii_read ( &lan78xx->mii, MII_BMCR ) ) < 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error reading phy ctrl register\n",
+ lan78xx );
+ return val;
+ }
+
+ val |= ( BMCR_ANENABLE | BMCR_ANRESTART );
+
+ if ( ( rc = mii_write ( &lan78xx->mii, MII_BMCR, val ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p error writing phy crtl register\n",
+ lan78xx );
+ return rc;
+ }
+
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * Endpoint operations
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Complete interrupt transfer
+ *
+ * @v ep USB endpoint
+ * @v iobuf I/O buffer
+ * @v rc Completion status code
+ */
+static void lan78xx_intr_complete ( struct usb_endpoint *ep,
+ struct io_buffer *iobuf, int rc ) {
+ struct lan78xx_device *lan78xx =
+ container_of ( ep, struct lan78xx_device, usbnet.intr );
+ struct net_device *netdev = lan78xx->netdev;
+ struct lan78xx_interrupt *intr;
+
+ /* Profile completions */
+ profile_start ( &lan78xx_intr_profiler );
+
+ /* Ignore packets cancelled when the endpoint closes */
+ if ( ! ep->open )
+ goto done;
+
+ /* Record USB errors against the network device */
+ if ( rc != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p interrupt failed: %s\n",
+ lan78xx, strerror ( rc ) );
+ DBGC_HDA ( lan78xx, 0, iobuf->data, iob_len ( iobuf ) );
+ netdev_rx_err ( netdev, NULL, rc );
+ goto done;
+ }
+
+ /* Extract interrupt data */
+ if ( iob_len ( iobuf ) != sizeof ( *intr ) ) {
+ DBGC ( lan78xx, "LAN78XX %p malformed interrupt\n",
+ lan78xx );
+ DBGC_HDA ( lan78xx, 0, iobuf->data, iob_len ( iobuf ) );
+ netdev_rx_err ( netdev, NULL, rc );
+ goto done;
+ }
+ intr = iobuf->data;
+
+ /* Record interrupt status */
+ lan78xx->int_sts = le32_to_cpu ( intr->int_sts );
+ profile_stop ( &lan78xx_intr_profiler );
+
+ done:
+ /* Free I/O buffer */
+ free_iob ( iobuf );
+}
+
+/** Interrupt endpoint operations */
+static struct usb_endpoint_driver_operations lan78xx_intr_operations = {
+ .complete = lan78xx_intr_complete,
+};
+
+/**
+ * Complete bulk IN transfer
+ *
+ * @v ep USB endpoint
+ * @v iobuf I/O buffer
+ * @v rc Completion status code
+ */
+static void lan78xx_in_complete ( struct usb_endpoint *ep,
+ struct io_buffer *iobuf, int rc ) {
+ struct lan78xx_device *lan78xx =
+ container_of ( ep, struct lan78xx_device, usbnet.in );
+ struct net_device *netdev = lan78xx->netdev;
+ struct lan78xx_rx_header *header;
+
+ /* Profile completions */
+ profile_start ( &lan78xx_in_profiler );
+
+ /* Ignore packets cancelled when the endpoint closes */
+ if ( ! ep->open ) {
+ free_iob ( iobuf );
+ return;
+ }
+
+ /* Record USB errors against the network device */
+ if ( rc != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p bulk IN failed: %s\n",
+ lan78xx, strerror ( rc ) );
+ goto err;
+ }
+
+ /* Sanity check */
+ if ( iob_len ( iobuf ) < ( sizeof ( *header ) ) ) {
+ DBGC ( lan78xx, "LAN78XX %p underlength bulk IN\n",
+ lan78xx );
+ DBGC_HDA ( lan78xx, 0, iobuf->data, iob_len ( iobuf ) );
+ rc = -EINVAL;
+ goto err;
+ }
+
+ /* Strip header */
+ header = iobuf->data;
+ iob_pull ( iobuf, sizeof ( *header ) );
+
+ /* Check for errors */
+ if ( header->command_a & cpu_to_le32 ( LAN78XX_RX_CMDA_RED ) ) {
+ DBGC ( lan78xx, "LAN78XX %p receive error (%08x):\n",
+ lan78xx, le32_to_cpu ( header->command_a ) );
+ DBGC_HDA ( lan78xx, 0, iobuf->data, iob_len ( iobuf ) );
+ rc = -EIO;
+ goto err;
+ }
+
+ /* Hand off to network stack */
+ netdev_rx ( netdev, iob_disown ( iobuf ) );
+
+ profile_stop ( &lan78xx_in_profiler );
+ return;
+
+ err:
+ /* Hand off to network stack */
+ netdev_rx_err ( netdev, iob_disown ( iobuf ), rc );
+}
+
+/** Bulk IN endpoint operations */
+static struct usb_endpoint_driver_operations lan78xx_in_operations = {
+ .complete = lan78xx_in_complete,
+};
+
+/**
+ * Transmit packet
+ *
+ * @v lan78xx LAN78xx device
+ * @v iobuf I/O buffer
+ * @ret rc Return status code
+ */
+static int lan78xx_out_transmit ( struct lan78xx_device *lan78xx,
+ struct io_buffer *iobuf ) {
+ struct lan78xx_tx_header *header;
+ size_t len = iob_len ( iobuf );
+ int rc;
+
+ /* Profile transmissions */
+ profile_start ( &lan78xx_out_profiler );
+
+ /* Prepend header */
+ if ( ( rc = iob_ensure_headroom ( iobuf, sizeof ( *header ) ) ) != 0 )
+ return rc;
+ header = iob_push ( iobuf, sizeof ( *header ) );
+ header->command_a = cpu_to_le32 ( LAN78XX_TX_FCS | len );
+ header->command_b = 0;
+
+ /* Enqueue I/O buffer */
+ if ( ( rc = usb_stream ( &lan78xx->usbnet.out, iobuf, 0 ) ) != 0 )
+ return rc;
+
+ profile_stop ( &lan78xx_out_profiler );
+ return 0;
+}
+
+/**
+ * Complete bulk OUT transfer
+ *
+ * @v ep USB endpoint
+ * @v iobuf I/O buffer
+ * @v rc Completion status code
+ */
+static void lan78xx_out_complete ( struct usb_endpoint *ep,
+ struct io_buffer *iobuf, int rc ) {
+ struct lan78xx_device *lan78xx =
+ container_of ( ep, struct lan78xx_device, usbnet.out );
+ struct net_device *netdev = lan78xx->netdev;
+
+ /* Report TX completion */
+ netdev_tx_complete_err ( netdev, iobuf, rc );
+}
+
+/** Bulk OUT endpoint operations */
+static struct usb_endpoint_driver_operations lan78xx_out_operations = {
+ .complete = lan78xx_out_complete,
+};
+
+/******************************************************************************
+ *
+ * Network device interface
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Open network device
+ *
+ * @v netdev Network device
+ * @ret rc Return status code
+ */
+static int lan78xx_open ( struct net_device *netdev ) {
+ struct lan78xx_device *lan78xx = netdev->priv;
+ union lan78xx_mac mac;
+ uint32_t reg;
+ int rc;
+
+ /* Clear stored interrupt status */
+ lan78xx->int_sts = 0;
+
+ /* Copy MAC address */
+ memset ( &mac, 0, sizeof ( mac ) );
+ memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
+
+ /* Configure bulk IN empty response */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_USB_CFG0,
+ ® ) ) != 0 )
+ goto err_usb_cfg0;
+
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_USB_CFG0,
+ reg | LAN78XX_USB_CFG0_BIR) ) != 0 )
+ goto err_usb_cfg0;
+
+ /* Open USB network device */
+ if ( ( rc = usbnet_open ( &lan78xx->usbnet ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not open: %s\n",
+ lan78xx, strerror ( rc ) );
+ goto err_open;
+ }
+
+ /* Configure interrupt endpoint */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_INT_EP_CTL,
+ ( LAN78XX_INT_EP_CTL_RDFO_EN |
+ LAN78XX_INT_EP_CTL_PHY_EN ) ) ) != 0 )
+ goto err_int_ep_ctl;
+
+ /* Configure bulk IN delay */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_BULK_IN_DLY,
+ LAN78XX_BULK_IN_DLY_SET ( 0 ) ) ) != 0 )
+ goto err_bulk_in_dly;
+
+ /* Configure receive filters */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_RFE_CTL,
+ ( LAN78XX_RFE_CTL_AB |
+ LAN78XX_RFE_CTL_AM ) ) ) != 0 )
+ goto err_rfe_ctl;
+
+ /* Configure receive FIFO */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_FCT_RX_CTL,
+ ( LAN78XX_FCT_RX_CTL_EN |
+ LAN78XX_FCT_RX_CTL_BAD ) ) ) != 0 )
+ goto err_fct_rx_ctl;
+
+ /* Configure transmit FIFO */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_FCT_TX_CTL,
+ LAN78XX_FCT_TX_CTL_EN ) ) != 0 )
+ goto err_fct_tx_ctl;
+
+ /* Write MAC address high register */
+ if ( ( rc = lan78xx_raw_writel ( lan78xx, LAN78XX_RX_ADDRH,
+ mac.addr.h ) ) != 0 )
+ goto err_rx_addrh;
+
+ /* Write MAC address low register */
+ if ( ( rc = lan78xx_raw_writel ( lan78xx, LAN78XX_RX_ADDRL,
+ mac.addr.l ) ) != 0 )
+ goto err_rx_addrl;
+
+ /* Write MAC address perfect filter high register */
+ mac.addr.h |= cpu_to_le32 ( LAN78XX_ADDR_FILTH_VALID );
+ if ( ( rc = lan78xx_raw_writel ( lan78xx, LAN78XX_ADDR_FILTH ( 0 ),
+ mac.addr.h ) ) != 0 )
+ goto err_addr_filth;
+
+ /* Write MAC address perfect filter low register */
+ if ( ( rc = lan78xx_raw_writel ( lan78xx, LAN78XX_ADDR_FILTL ( 0 ),
+ mac.addr.l ) ) != 0 )
+ goto err_addr_filtl;
+
+ /* Initialize phy */
+ if ( (rc = lan78xx_phy_init( lan78xx ) ) != 0 )
+ goto err_phy_init;
+
+ /* Configure MAC automatic speed, duplex and polarity */
+ if ( ( rc = lan78xx_readl ( lan78xx, LAN78XX_MAC_CR,
+ ® ) ) != 0 )
+ goto err_mac_cr;
+
+ reg |= (LAN78XX_MAC_CR_ADP | LAN78XX_MAC_CR_ADD |
+ LAN78XX_MAC_CR_ASD);
+
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MAC_CR,
+ reg ) ) != 0 )
+ goto err_mac_cr;
+
+ /* Configure transmit datapath */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MAC_TX,
+ LAN78XX_MAC_TX_EN ) ) != 0 )
+ goto err_mac_tx;
+
+ /* Configure receive datapath */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_MAC_RX,
+ ( LAN78XX_MAC_RX_MAX_SIZE_DEFAULT |
+ LAN78XX_MAC_RX_FCS |
+ LAN78XX_MAC_RX_EN ) ) ) != 0 )
+ goto err_mac_rx;
+
+ /* Enable PHY interrupts */
+ if ( ( rc = mii_write ( &lan78xx->mii, LAN78XX_MII_PHY_INTR_MASK,
+ ( LAN78XX_PHY_INTR_ENABLE |
+ LAN78XX_PHY_INTR_LINK_CHANGE ) ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not set PHY interrupt "
+ "mask: %s\n", lan78xx, strerror ( rc ) );
+ goto err_phy_intr_mask;
+ }
+
+ /* Update link status */
+ lan78xx_check_link ( lan78xx );
+
+ return 0;
+
+ err_phy_intr_mask:
+ err_addr_filtl:
+ err_addr_filth:
+ err_phy_init:
+ err_mac_cr:
+ err_rx_addrl:
+ err_rx_addrh:
+ err_mac_tx:
+ err_mac_rx:
+ err_fct_tx_ctl:
+ err_fct_rx_ctl:
+ err_rfe_ctl:
+ err_bulk_in_dly:
+ err_int_ep_ctl:
+ usbnet_close ( &lan78xx->usbnet );
+ err_usb_cfg0:
+ err_open:
+ lan78xx_reset ( lan78xx );
+ return rc;
+}
+
+/**
+ * Close network device
+ *
+ * @v netdev Network device
+ */
+static void lan78xx_close ( struct net_device *netdev ) {
+ struct lan78xx_device *lan78xx = netdev->priv;
+
+ /* Close USB network device */
+ usbnet_close ( &lan78xx->usbnet );
+
+ /* Reset device */
+ lan78xx_reset ( lan78xx );
+}
+
+/**
+ * Transmit packet
+ *
+ * @v netdev Network device
+ * @v iobuf I/O buffer
+ * @ret rc Return status code
+ */
+static int lan78xx_transmit ( struct net_device *netdev,
+ struct io_buffer *iobuf ) {
+ struct lan78xx_device *lan78xx = netdev->priv;
+ int rc;
+
+ /* Transmit packet */
+ if ( ( rc = lan78xx_out_transmit ( lan78xx, iobuf ) ) != 0 )
+ return rc;
+
+ return 0;
+}
+
+/**
+ * Poll for completed and received packets
+ *
+ * @v netdev Network device
+ */
+static void lan78xx_poll ( struct net_device *netdev ) {
+ struct lan78xx_device *lan78xx = netdev->priv;
+ uint32_t int_sts;
+ int rc;
+
+ /* Poll USB bus */
+ usb_poll ( lan78xx->bus );
+
+ /* Refill endpoints */
+ if ( ( rc = usbnet_refill ( &lan78xx->usbnet ) ) != 0 )
+ netdev_rx_err ( netdev, NULL, rc );
+
+ /* Do nothing more unless there are interrupts to handle */
+ int_sts = lan78xx->int_sts;
+ if ( ! int_sts )
+ return;
+
+ /* Check link status if applicable */
+ if ( int_sts & LAN78XX_INT_STS_PHY_INT ) {
+ lan78xx_check_link ( lan78xx );
+ int_sts &= ~LAN78XX_INT_STS_PHY_INT;
+ }
+
+ /* Record RX FIFO overflow if applicable */
+ if ( int_sts & LAN78XX_INT_STS_RDFO_INT ) {
+ DBGC2 ( lan78xx, "LAN78XX %p RX FIFO overflowed\n",
+ lan78xx );
+ netdev_rx_err ( netdev, NULL, -ENOBUFS );
+ int_sts &= ~LAN78XX_INT_STS_RDFO_INT;
+ }
+
+ /* Check for unexpected interrupts */
+ if ( int_sts ) {
+ DBGC ( lan78xx, "LAN78XX %p unexpected interrupt %#08x\n",
+ lan78xx, int_sts );
+ netdev_rx_err ( netdev, NULL, -ENOTTY );
+ }
+
+ /* Clear interrupts */
+ if ( ( rc = lan78xx_writel ( lan78xx, LAN78XX_INT_STS,
+ lan78xx->int_sts ) ) != 0 )
+ netdev_rx_err ( netdev, NULL, rc );
+ lan78xx->int_sts = 0;
+}
+
+/** LAN78xx network device operations */
+static struct net_device_operations lan78xx_operations = {
+ .open = lan78xx_open,
+ .close = lan78xx_close,
+ .transmit = lan78xx_transmit,
+ .poll = lan78xx_poll,
+};
+
+/******************************************************************************
+ *
+ * USB interface
+ *
+ ******************************************************************************
+ */
+
+/**
+ * Probe device
+ *
+ * @v func USB function
+ * @v config Configuration descriptor
+ * @ret rc Return status code
+ */
+static int lan78xx_probe ( struct usb_function *func,
+ struct usb_configuration_descriptor *config ) {
+ struct usb_device *usb = func->usb;
+ struct net_device *netdev;
+ struct lan78xx_device *lan78xx;
+ int rc;
+
+ /* Allocate and initialise structure */
+ netdev = alloc_etherdev ( sizeof ( *lan78xx ) );
+ if ( ! netdev ) {
+ rc = -ENOMEM;
+ goto err_alloc;
+ }
+ netdev_init ( netdev, &lan78xx_operations );
+ netdev->dev = &func->dev;
+ lan78xx = netdev->priv;
+ memset ( lan78xx, 0, sizeof ( *lan78xx ) );
+ lan78xx->usb = usb;
+ lan78xx->bus = usb->port->hub->bus;
+ lan78xx->netdev = netdev;
+ usbnet_init ( &lan78xx->usbnet, func, &lan78xx_intr_operations,
+ &lan78xx_in_operations, &lan78xx_out_operations );
+ usb_refill_init ( &lan78xx->usbnet.intr, 0, 0, LAN78XX_INTR_MAX_FILL );
+ usb_refill_init ( &lan78xx->usbnet.in, 0, LAN78XX_IN_MTU,
+ LAN78XX_IN_MAX_FILL );
+ mii_init ( &lan78xx->mii, &lan78xx_mii_operations );
+ DBGC ( lan78xx, "LAN78XX %p on %s\n", lan78xx, func->name );
+
+ /* Describe USB network device */
+ if ( ( rc = usbnet_describe ( &lan78xx->usbnet, config ) ) != 0 ) {
+ DBGC ( lan78xx, "LAN78XX %p could not describe: %s\n",
+ lan78xx, strerror ( rc ) );
+ goto err_describe;
+ }
+
+ /* Reset device */
+ if ( ( rc = lan78xx_reset ( lan78xx ) ) != 0 )
+ goto err_reset;
+
+ /* Read MAC address */
+ if ( ( rc = lan78xx_get_mac_address ( lan78xx,
+ netdev->hw_addr ) ) != 0 )
+ goto err_eeprom_read;
+
+ /* Register network device */
+ if ( ( rc = register_netdev ( netdev ) ) != 0 )
+ goto err_register;
+
+ usb_func_set_drvdata ( func, netdev );
+ return 0;
+
+ unregister_netdev ( netdev );
+ err_register:
+ err_eeprom_read:
+ err_reset:
+ err_describe:
+ netdev_nullify ( netdev );
+ netdev_put ( netdev );
+ err_alloc:
+ return rc;
+}
+
+/**
+ * Remove device
+ *
+ * @v func USB function
+ */
+static void lan78xx_remove ( struct usb_function *func ) {
+ struct net_device *netdev = usb_func_get_drvdata ( func );
+
+ unregister_netdev ( netdev );
+ netdev_nullify ( netdev );
+ netdev_put ( netdev );
+}
+
+/** LAN78xx device IDs */
+static struct usb_device_id lan78xx_ids[] = {
+ {
+ .name = "lan7800",
+ .vendor = 0x0424,
+ .product = 0x7800,
+ },
+ {
+ .name = "lan7850",
+ .vendor = 0x0424,
+ .product = 0x7850,
+ },
+};
+
+/** LAN78xx driver */
+struct usb_driver lan78xx_driver __usb_driver = {
+ .ids = lan78xx_ids,
+ .id_count = ( sizeof ( lan78xx_ids ) / sizeof ( lan78xx_ids[0] ) ),
+ .class = USB_CLASS_ID ( 0xff, 0x00, 0xff ),
+ .score = USB_SCORE_NORMAL,
+ .probe = lan78xx_probe,
+ .remove = lan78xx_remove,
+};
diff --git a/src/drivers/net/lan78xx.h b/src/drivers/net/lan78xx.h
new file mode 100644
index 0000000..b02dbd0
--- /dev/null
+++ b/src/drivers/net/lan78xx.h
@@ -0,0 +1,285 @@
+#ifndef _LAN78XX_H
+#define _LAN78XX_H
+
+/** @file
+ *
+ * Microchip LAN78xx USB 3.0 to Ethernet driver
+ *
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
+
+#include <ipxe/usb.h>
+#include <ipxe/usbnet.h>
+#include <ipxe/if_ether.h>
+#include <ipxe/mii.h>
+
+/** Register write command */
+#define LAN78XX_REGISTER_WRITE \
+ ( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
+ USB_REQUEST_TYPE ( 0xa0 ) )
+
+/** Register read command */
+#define LAN78XX_REGISTER_READ \
+ ( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
+ USB_REQUEST_TYPE ( 0xa1 ) )
+
+/** Get statistics command */
+#define LAN78XX_GET_STATISTICS \
+ ( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
+ USB_REQUEST_TYPE ( 0xa2 ) )
+
+/** Chip id register */
+#define LAN78XX_ID_REV 0x0
+#define LAN78XX_ID_LAN7800 0x7800
+#define LAN78XX_ID_LAN7850 0x7850
+#define LAN78XX_ID_GET(chip_id) \
+ ( (chip_id) >> 16 )
+
+/** Interrupt status register */
+#define LAN78XX_INT_STS 0x00c
+#define LAN78XX_INT_STS_CLEAR_ALL 0xFFFFFFFFUL
+#define LAN78XX_INT_STS_RDFO_INT 0x00400000UL /**< RX FIFO overflow */
+#define LAN78XX_INT_STS_PHY_INT 0x00020000UL /**< PHY interrupt */
+
+/** Hardware configuration register */
+#define LAN78XX_HW_CFG 0x010
+#define LAN78XX_HW_CFG_MEF 0x00000010UL /**< Soft lite reset */
+#define LAN78XX_HW_CFG_LRST 0x00000002UL /**< Soft lite reset */
+#define LAN78XX_HW_CFG_LED0_EN 0x00100000UL /**< Led0 enable */
+#define LAN78XX_HW_CFG_LED1_EN 0x00200000UL /**< Led1 enable */
+
+#define LAN78XX_PMT_CTL 0x014
+#define LAN78XX_PMT_CTL_DEV_RDY 0x00000080UL
+#define LAN78XX_PMT_CTL_PHY_RST 0x00000010UL
+
+/** EEPROM command register */
+#define LAN78XX_E2P_CMD 0x040
+#define LAN78XX_E2P_CMD_EPC_BSY 0x80000000UL /**< EPC busy */
+#define LAN78XX_E2P_CMD_EPC_TIMEOUT 0x00000400UL
+#define LAN78XX_E2P_CMD_EPC_CMD_READ 0x00000000UL /**< READ command */
+#define LAN78XX_E2P_CMD_EPC_ADDR(addr) ( ( addr & 0x1ff ) ) /**< EPC address */
+
+/** EEPROM data register */
+#define LAN78XX_E2P_DATA 0x044
+#define LAN78XX_E2P_DATA_GET(e2p_data) \
+ ( ( (e2p_data) >> 0 ) & 0xff ) /**< EEPROM data */
+
+/** MAC address EEPROM address */
+#define LAN78XX_EEPROM_MAC 0x01
+
+/** OTP registers */
+#define LAN78XX_OTP_BASE_ADDR 0x00001000
+
+#define LAN78XX_OTP_PWR_DN ( LAN78XX_OTP_BASE_ADDR + 4 * 0x00 )
+#define LAN78XX_OTP_PWR_DN_PWRDN ( 0x01 )
+
+#define LAN78XX_OTP_ADDR_HIGH ( LAN78XX_OTP_BASE_ADDR + 4 * 0x01 )
+#define LAN78XX_OTP_ADDR_HIGH_1_0(addr) ( ( ( addr >> 8 ) & 0x3 ) )
+
+#define LAN78XX_OTP_ADDR_LOW ( LAN78XX_OTP_BASE_ADDR + 4 * 0x02 )
+#define LAN78XX_OTP_ADDR_LOW_7_0(addr) ( ( addr & 0xff ) )
+
+#define LAN78XX_OTP_RD_DATA ( LAN78XX_OTP_BASE_ADDR + 4 * 0x06 )
+#define LAN78XX_OTP_DATA_GET(otp_data) \
+ ( ( ( otp_data ) >> 0 ) & 0xff ) /**< OTP data */
+
+#define LAN78XX_OTP_FUNC_CMD ( LAN78XX_OTP_BASE_ADDR + 4 * 0x08 )
+#define LAN78XX_OTP_FUNC_CMD_READ ( 0x01 )
+
+#define LAN78XX_OTP_CMD_GO ( LAN78XX_OTP_BASE_ADDR + 4 * 0x0A )
+#define LAN78XX_OTP_CMD_GO_GO ( 0x01 )
+
+#define LAN78XX_OTP_STATUS ( LAN78XX_OTP_BASE_ADDR + 4 * 0x0C )
+#define LAN78XX_OTP_STATUS_BUSY ( 0x01 )
+
+/** OTP signature (first byte) 0xF3: otp starts from offset 0 */
+#define LAN78XX_OTP_INDICATOR_1 ( 0xF3 )
+/** OTP signature (first byte) 0xF7: otp starts from offset 0x100 */
+#define LAN78XX_OTP_INDICATOR_2 ( 0xF7 )
+
+/** Bulk In Empty response setting */
+#define LAN78XX_USB_CFG0 0x080
+#define LAN78XX_USB_CFG0_BIR 0x00000040UL
+
+/** Burst cap register */
+#define LAN78XX_BURST_CAP 0x090
+
+/** Bulk IN delay register */
+#define LAN78XX_BULK_IN_DLY 0x094
+#define LAN78XX_BULK_IN_DLY_SET(ticks) \
+ ( ( ticks ) << 0 ) /**< Delay / 16.7ns */
+
+/** Interrupt endpoint control register */
+#define LAN78XX_INT_EP_CTL 0x098
+#define LAN78XX_INT_EP_CTL_RDFO_EN 0x00400000UL /**< RX FIFO overflow */
+#define LAN78XX_INT_EP_CTL_PHY_EN 0x00020000UL /**< PHY interrupt */
+
+/** Receive filtering engine control register */
+#define LAN78XX_RFE_CTL 0x0b0
+#define LAN78XX_RFE_CTL_AB 0x00000400UL /**< Accept broadcast */
+#define LAN78XX_RFE_CTL_AM 0x00000200UL /**< Accept multicast */
+#define LAN78XX_RFE_CTL_AU 0x00000100UL /**< Accept unicast */
+
+/** FIFO controller RX FIFO control register */
+#define LAN78XX_FCT_RX_CTL 0x0c0
+#define LAN78XX_FCT_RX_CTL_EN 0x80000000UL /**< FCT RX enable */
+#define LAN78XX_FCT_RX_CTL_BAD 0x02000000UL /**< Store bad frames */
+
+/** FIFO controller TX FIFO control register */
+#define LAN78XX_FCT_TX_CTL 0x0c4
+#define LAN78XX_FCT_TX_CTL_EN 0x80000000UL /**< FCT TX enable */
+
+/** MAC control register */
+#define LAN78XX_MAC_CR 0x100
+#define LAN78XX_MAC_CR_ADP 0x00002000UL /**< Duplex Polarity */
+#define LAN78XX_MAC_CR_ADD 0x00001000UL /**< Duplex Detection */
+#define LAN78XX_MAC_CR_ASD 0x00000800UL /**< Speed Detection */
+
+/** MAC receive register */
+#define LAN78XX_MAC_RX 0x104
+#define LAN78XX_MAC_RX_MAX_SIZE(mtu) \
+ ( ( mtu ) << 16 ) /**< Max frame size */
+#define LAN78XX_MAC_RX_MAX_SIZE_DEFAULT \
+ LAN78XX_MAC_RX_MAX_SIZE ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
+#define LAN78XX_MAC_RX_FCS 0x00000010UL /**< FCS stripping */
+#define LAN78XX_MAC_RX_EN 0x00000001UL /**< RX enable */
+
+/** MAC transmit register */
+#define LAN78XX_MAC_TX 0x108
+#define LAN78XX_MAC_TX_EN 0x00000001UL /**< TX enable */
+
+/** MAC receive address high register */
+#define LAN78XX_RX_ADDRH 0x118
+
+/** MAC receive address low register */
+#define LAN78XX_RX_ADDRL 0x11c
+
+/** MII access register */
+#define LAN78XX_MII_ACCESS 0x120
+#define LAN78XX_MII_ACCESS_PHY_ADDR(addr) \
+ ( ( addr ) << 11 ) /**< PHY address */
+#define LAN78XX_MII_ACCESS_MIIRINDA(addr) \
+ ( (addr) << 6 ) /**< MII register */
+#define LAN78XX_MII_ACCESS_MIIWNR 0x00000002UL /**< MII write */
+#define LAN78XX_MII_ACCESS_MIIBZY 0x00000001UL /**< MII busy */
+
+/** MII data register */
+#define LAN78XX_MII_DATA 0x124
+#define LAN78XX_MII_DATA_SET(data) ( (data) << 0 ) /**< Set data */
+#define LAN78XX_MII_DATA_GET(mii_data) \
+ ( ( ( mii_data ) >> 0 ) & 0xffff ) /**< Get data */
+
+/** PHY interrupt mask MII register */
+#define LAN78XX_MII_PHY_INTR_MASK 25
+#define LAN78XX_PHY_INTR_ENABLE 0x8000
+
+/** PHY interrupt source MII register */
+#define LAN78XX_MII_PHY_INTR_SOURCE 26
+
+/** PHY interrupt mask and status: auto-negotiation complete */
+#define LAN78XX_PHY_INTR_ANEG_DONE 0x0400
+
+/** PHY interrupt mask and status: link status change */
+#define LAN78XX_PHY_INTR_LINK_CHANGE 0x2000
+
+/** MAC address perfect filter N high register */
+#define LAN78XX_ADDR_FILTH(n) ( 0x400 + ( 8 * (n) ) )
+#define LAN78XX_ADDR_FILTH_VALID 0x80000000UL /**< Address valid */
+
+/** MAC address perfect filter N low register */
+#define LAN78XX_ADDR_FILTL(n) ( 0x404 + ( 8 * (n) ) )
+
+/** MAC address */
+union lan78xx_mac {
+ /** MAC receive address registers */
+ struct {
+ /** MAC receive address low register */
+ uint32_t l;
+ /** MAC receive address high register */
+ uint32_t h;
+ } __attribute__ (( packed )) addr;
+ /** Raw MAC address */
+ uint8_t raw[ETH_ALEN];
+};
+
+/** Receive packet header */
+struct lan78xx_rx_header {
+ /** Rx command A*/
+ uint32_t command_a;
+ /** Rx command B */
+ uint32_t command_b;
+ /** Rx command C */
+ uint16_t command_c;
+} __attribute__ (( packed ));
+
+/** Receive error detected */
+#define LAN78XX_RX_CMDA_RED 0x00400000UL
+
+/** Transmit packet header */
+struct lan78xx_tx_header {
+ /** Tx command A */
+ uint32_t command_a;
+ /** Tx command B */
+ uint32_t command_b;
+} __attribute__ (( packed ));
+
+/** Insert frame checksum and pad */
+#define LAN78XX_TX_FCS 0x00400000UL
+
+/** Interrupt packet format */
+struct lan78xx_interrupt {
+ /** Current value of INT_STS register */
+ uint32_t int_sts;
+} __attribute__ (( packed ));
+
+/** A LAN78xx network device */
+struct lan78xx_device {
+ /** USB device */
+ struct usb_device *usb;
+ /** USB bus */
+ struct usb_bus *bus;
+ /** Network device */
+ struct net_device *netdev;
+ /** USB network device */
+ struct usbnet_device usbnet;
+ /** MII interface */
+ struct mii_interface mii;
+ /** Interrupt status */
+ uint32_t int_sts;
+ /** Phy address */
+ uint8_t phy_addr;
+ /** Chip id */
+ uint32_t chip_id;
+};
+
+/** Device reset delay */
+#define LAN78XX_RESET_MAX_WAIT_MS 100
+
+/** Maximum time to wait for EEPROM (in milliseconds) */
+#define LAN78XX_EEPROM_MAX_WAIT_MS 100
+
+/** Maximum time to wait for OTP (in milliseconds) */
+#define LAN78XX_OTP_MAX_WAIT_MS 100
+
+/** Maximum time to wait for MII (in milliseconds) */
+#define LAN78XX_MII_MAX_WAIT_MS 100
+
+/** Interrupt maximum fill level
+ *
+ * This is a policy decision.
+ */
+#define LAN78XX_INTR_MAX_FILL 2
+
+/** Bulk IN maximum fill level
+ *
+ * This is a policy decision.
+ */
+#define LAN78XX_IN_MAX_FILL 8
+
+/** Bulk IN buffer size */
+#define LAN78XX_IN_MTU \
+ ( sizeof ( struct lan78xx_rx_header ) + \
+ ETH_FRAME_LEN + 4 /* possible VLAN header */ )
+
+#endif /* _LAN78XX_H */
--
1.7.9.5
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