<p></p>
<blockquote>
<p>What problem is this actually solving?</p>
</blockquote>
<p>Allow me to demonstrate:</p>
<pre><code>$ echo && cat Makefile.bad && echo && EMBED=foobar make -f Makefile.bad && echo && cat Makefile.good && EMBED=foobar make -f Makefile.good 

EMBED := $(EMBEDDED_IMAGE)

.PHONY: all
all:
        echo "EMBEDDED_IMAGE: $(EMBEDDED_IMAGE)"
        echo "EMBED: $(EMBED)"


echo "EMBEDDED_IMAGE: "
EMBEDDED_IMAGE: 
echo "EMBED: "
EMBED: 

EMBED ?= $(EMBEDDED_IMAGE)

.PHONY: all
all:
        echo "EMBEDDED_IMAGE: $(EMBEDDED_IMAGE)"
        echo "EMBED: $(EMBED)"

echo "EMBEDDED_IMAGE: "
EMBEDDED_IMAGE: 
echo "EMBED: foobar"
EMBED: foobar
</code></pre>
<p>When the definition of the shell variable <code>EMBED</code> precedes <code>make</code>, <code>Makefile.good</code> shows the effect and <code>Makefile.bad</code> does not.</p>
<blockquote>
<p>Any variables specified in the <code>make</code> command line will override assignments within the Makefile. Building with <code>make EMBED=...</code> works with no problems already.</p>
</blockquote>
<p>You're not wrong: <code>make EMBED=...</code> works. What doesn't work is <code>EMBED=... make</code> or any combination of exporting a shell variable for later consumption by a <code>make</code> invocation. For reasons that I have yet to dig out of the GNU Make manual, consuming that variable definition only works when it appears as a argument to the <code>make</code> command.</p>
<p>Strictly speaking, it's not incorrect to accept only variable assignments that happen to follow the command, but it will confuse others (like me) that assume the <code>EMBED</code> should behave like a shell variable when the immediate assignment prevents exactly that.</p>

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